Processador Intel Future Roadmaps

[Dark Kaeser]

Intel Reports Q4 2021 and FY 2021 Earnings: Ending 2021 On A High Note​

Starting with quarterly results, for the fourth quarter of 2021, Intel reported $20.5B in revenue, which is a small jump of 3% over the year-ago quarter. Intel has managed to improve upon an already strong Q4’20, which is always welcome news for the biggest quarter of the year for the company. Intel’s net income hasn’t fared quite as well, however, and continues to degrade from Intel’s highs of a few years ago. For the most recent quarter Intel booked $4.6B in profit, down $1.3B (21%) from the year-ago quarter.

Data center revenue was up 20% to $7.3B, with both platform volumes and ASPs rising versus the year-ago quarter. Intel cites strong enterprise demand – especially from government customers – as helping to drive DCG’s improved performance.

Unfortunately for all the good news Intel has to report, the hero of 2020, the Client Computing Group (CCG) was the odd man out for Q4’21, becoming the only group to see revenue fall versus the year-ago quarter. Overall CCG revenue fell 7%, with processor revenues falling 5% while the group’s adjacencies fell 28%. In explaining the difference, Intel is attributing the drop in revenue to “ecosystem constraints” as well as the ramp-down of their cellular modem business.

Overall the company booked $79.0B in revenue for the year, 1% more than 2020. Intel’s overall net income didn’t fare quite as well– dogged by issues similar to their Q4 earnings – but the company is still going out on $19.9B in net income for the year, a 5% drop from 2020.
Gross margins for the entire year were 55.4%, down 0.6 percentage points from 2020. As with Intel’s quarterly results, this is generally tied to the company’s R&D spending and other manufacturing investments; Intel is giving up profitability now in hopes of growing the company down the line.

https://www.anandtech.com/show/1723...d-fy-2021-earnings-ending-2021-on-a-high-note

 

[Dark Kaeser]

Esta apresentação da Intel

https://twitter.com/i/web/status/1494399500500312064

ele entretanto fez um artigo, em alemão, mas resumindo

https://www.hardwareluxx.de/index.p...r-weitere-details-zur-fertigungs-roadmap.html

Intel Goes Full XPU: Falcon Shores to Combine x86 and Xe For Supercomputers​

At a very high level, Falcon Shores appears to be an HPC-grade APU/SoC/XPU for servers. While Intel is offering only the barest of details at this time, the company is being upfront in that they are combining x86 CPU and Xe GPU hardware into a single chip, with an eye on leveraging the synergy between the two. And, given the mention of advanced packaging technologies, it’s a safe bet that Intel has something more complex than a monolithic die planned, be it separate CPU/GPU tiles, HBM memory (e.g. Sapphire Rapids), or something else entirely.

Diving a bit deeper, while integrating discrete components often pays benefits over the long run, the nature of the announcement strongly indicates that there’s more to Intel’s plan here than just integrating a CPU and GPU into a single chip (something they already do today in consumer parts). Rather, the presentation from Raja Koduri, Intel’s SVP and GM of the Accelerated Computing Systems and Graphics (AXG) Group, makes it clear that Intel is looking to go after the market for HPC users with absolutely massive datasets – the kind that can’t easily fit into the relatively limited memory capacity of a discrete GPU.

Meanwhile, Intel is also touting Falcon Shores as offering a flexible ratio between x86 and Xe cores. The devil is in the details here, but at a high level it sounds like the company is looking at offering multiple SKUs with different numbers of cores – likely enabled by varying the number of x86 and Xe titles.

https://www.anandtech.com/show/1726...ores-to-combine-x86-and-xe-for-supercomputers

 

[Dark Kaeser]

Finalmente saiu o roadmap até 2024 para os CPU

https://twitter.com/i/web/status/1494439075864010759

https://twitter.com/i/web/status/1494448784440496137

EDIT: Anandtech já fez update ao Xeon Roadmap

Intel Discloses Multi-Generation Xeon Scalable Roadmap: New E-Core Only Xeons in 2024​

Looking beyond Sapphire Rapids, Intel is finally putting materials into the public to showcase what is coming up on the roadmap. After Sapphire Rapids, we will have a platform compatible Emerald Rapids Xeon Scalable product, also built on Intel 7, in 2023. Given the naming conventions, Emerald Rapids is likely to be the 5th Generation.

Emerald Rapids (EMR), as with some other platform updates, is expected to capture the low hanging fruit from the Sapphire Rapids design to improve performance, as well as updates from the manufacturing. With platform compatibility, it means Emerald will have the same support when it comes to PCIe lanes, CPU-to-CPU connectivity, DRAM, CXL, and other IO features. We’re likely to see updated accelerators too. Exactly what the silicon will look like however is still an unknown. As we’re still new in Intel’s tiled product portfolio, there’s a good chance it will be similar to Sapphire Rapids, but it could equally be something new, such as what Intel has planned for the generation after.

My other question to Intel was about Hybrid CPU designs – if Intel was now going to make P-core tiles and E-core tiles, what’s stopping a combined product with both? Intel stated that their customers prefer uni-core designs in this market as the needs from customer to customer differ. If one customer prefers an 80/20 split on P-cores to E-cores, there’s another customer that prefers a 20/80 split. Having a wide array of products for each different ratio doesn’t make sense, and customers already investigating this are finding out that the software works better with a homogeneous arrangement, instead split at the system level, rather than the socket level. So we’re not likely to see hybrid Xeons any time soon. (Ian: Which is a good thing.)

https://www.anandtech.com/show/1725...scalable-roadmap-new-ecore-only-xeons-in-2024

 

[Nemesis11]

Big.Little em servidores levanta outro problema. Previsibilidade. Com Big.Little torna isso bem mais complicado. Há casos até, em que desliga o Turbo ou se bloqueia o CPU num certo Clock, para se ter a maior previsibilidade possível.

Quanto ao Sierra Forest, é o que estava à espera. Um Processador para as grandes Clouds. O ultimo Altra e o Zen4c já apontavam para aí.

Quanto ao Falcon Shores, se calhar a Intel ainda terá um "Mega APU" no mercado consumidor antes da AMD.

 

[Dark Kaeser]

Na realidade a AMD só fará o Mega APU se alguém pagar por ele.

A Intel também já tem o seu "Custom Silicon", ainda há dias apresentaram um produto para esse mercado.

Nesta investor meeting, foi referido

Custom Compute Group – AXG’s Custom Compute Group will build tailored products for emerging workloads such as blockchain, supercomputing at the edge, premium infotainment for cars, immersive displays and more.

https://www.intel.com/content/www/u...technology-roadmaps-milestones.html#gs.q115hx


de há uma semana atrás

Blockchain and the New Custom Compute Group​

Our blockchain accelerator will ship later this year. We are engaged directly with customers that share our sustainability goals. Argo Blockchain, BLOCK (formerly known as Square) and GRIID Infrastructure are among our first customers for this upcoming product. This architecture is implemented on a tiny piece of silicon so that it has minimal impact to the supply of current products.

https://www.intel.com/content/www/u...lockchain-custom-compute-group.html#gs.q12071

Aparentemente este chip fará parte de uma apresentação, por parte da Intel, na ISSCC '22, que começa dia 20.

 

[nullus]

Acho que definitivamente ficou confirmado que Raptor Lake é apenas um refinamento dos Alder Lake com um upgrade do numero de threads.

https://twitter.com/i/web/status/1494449725025787912

Parece-me que a verdadeira competição dos zen4 vai chegar apenas quando sairem os Meteor Lake.

 

[Nemesis11]

Depende da performance do Zen4. Do que se fala do Raptor lake, o E cores passam de 8 para 16 e parece que vão aumentar a Cache L2 dos E e P Cores. De 2 para 4 MB em cada quadrante de E Cores e de 1,25 para 2 MB por cada P Core.
Os E cores parece que são "Gracemont Plus", por isso é provável que os P cores sejam apenas uma evolução.
É provável que o Zen4 seja um salto maior a nível de arquitectura, mas não quer dizer que tenham melhor performance.

Na realidade a AMD só fará o Mega APU se alguém pagar por ele.

Sim, é um produto que teria mais interesse para OEMs do que no mercado retail e por isso tens razão.
Pode ser que a Apple comece a fazer comichão a essas OEMs.

 

[Dark Kaeser]

Nem isso. Tal como este da Intel era dirigido ao mercado HPC, fazia parte do "Heterogeneous Processing" e foi um dois programas da AMD financiados pelo DoEnergy ou DoDefense, sendo que o outro era o interconnect, que provavelmente resultou no IF.

No ano passado voltaram à carga
https://www.google.com/amp/s/www.te...ator-to-be-paired-with-gpu-cache-chiplets?amp

E provavelmente já terão submetido outras.

 

[Nemesis11]

Já agora, não tinha reparado nestes slides da Intel:

O interessante deste Slide é que, não só tem o Sapphire Rapids, como tem o Sapphire Rapids com HBM. Além disso, tem o Milan e o Milan-X, um produto que a própria AMD aponta inicialmente para este mercado HPC.

Segundo Slide:

Comparação do Ponte Vecchio com a "Competição". Com uma barra de cor verde, acho que sei quem será aquela "Competição".

Colocar muito sal nestes Slides. Slides dos fabricantes são sempre muito parciais e a Intel tem bastante tradição nesse campo.

 

[Dark Kaeser]

Em relação ao último slide, há um problema, se o Ponte Vecchio sair apenas para o final do ano a competição pode ser a MI300

Já agora os slides da Investor Meeting

- Pat Gelsinger, CEO
https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-CEO.pdf

- David Zinsner CFO
https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-CFO.pdf

- Michelle Johnston Holthaus, EVP, General Manager Client Compute Group
https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-Client.pdf

- Sandra RIvera, EVP, General Manager, Data Center & AI Group
https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-Data-Center-AI.pdf

 

[Nemesis11]

Em relação ao último slide, há um problema, se o Ponte Vecchio sair apenas para o final do ano a competição pode ser a MI300

E o Hopper ou lá que nome terá, da nVidia.
No entanto, se o Ponte Vecchio não for o produto mais competitivo naquele mercado, não é grande problema. Nos últimos tempos a Intel tem lançado produtos que acho que são mais "balões de ensaio", do que produtos com o objectivo de se venderem em grandes quantidades e obter grandes lucros.
Exemplos: Lakefield, DG1. Este Ponte Vecchio está nessa categoria.
Mais importante serão os produtos que lhes seguirem.

 

[Dark Kaeser]

Sim este PVC será o MI100 da AMD (o primeiro CDNA) que também passou praticamente ao lado. O desafio de AMBOS é tirar o CUDA como "o software de facto para HPC", a AMD só concluiu isso há uns meses com o lançamento do ROCm 5.0 (o suporte estava no -dev branch) e a Intel com a OneAPI.

Mas agora que reparei nas imagens, no caso do SPR o Milan aparece com barras vermelhas, portanto neste caso, a barra a verde deve representar a Ampere GA100 e o Hopper deve sair para o 2º semestre.

EDIT: já agora, qual a probabilidade de ir parar à Intel?

https://twitter.com/i/web/status/1494667779626180608

 

[Nemesis11]

Alegadamente um Slide do Arrow Lake para o mercado mobile (Q4 2023/Q1 2024):

Parece que irá utilizar Intel N20A e TSMC 3nm.
6 P Cores + 8 E Cores + 320 EUs (Em menos de 80 mm²).

Parece que o alvo são os SOCs da Apple.

EDIT: A versão Desktop parece que irá ter 8 P Cores + 32 E Cores.

https://videocardz.com/newz/intel-a...ting-to-compete-with-apple-14-premium-laptops

 

[JPgod]

Será isso o mega APU que andamos a conversar? 320 EU?!?

Mas acho que 80mm2 é apenas o GPU

 

[Dark Kaeser]

Não, nada disso.

Este "Falcon Shores" será para o mercado servidor

Falcon Shores

“We are working on a brand new architecture codenamed Falcon Shores,” Koduri said. “Falcon Shores will bring x86 and Xe GPU acceleration together into a Xeon socket, taking advantage of next-generation packaging, memory, and I/O technologies, giving huge performance and efficiency improvements for systems computing large datasets and training gigantic AI models.”

https://www.hpcwire.com/2022/02/18/...n-shores-cpu-gpu-combo-architecture-for-2024/

Mas esse ADL-S é o vislumbre do "futuro"? Ou seja agora a Intel vai ter apenas 8 P cores e vai aumentando o número de E cores?!

Além disso relativamente ao iGPU, esse "leak" contraria o "leak" dos drivers da própria Intel, de Dezembro,

Furthermore, it lists Raptor Lake-S (RPLS), Meteor Lake (MTL), Arrow Lake (ARL), and Lunar Lake (LNL) in the config files, alongside Device PCI IDs, this can be used later to pinpoint leaks. It looks like this driver (released 2 days ago), only lists two DG3 GPUs thus far. This suggests that the DG3 is still far from being ready. The DG3 GPU family is to be used by Arc Battlemage desktop and mobile GPUs.

The files also confirm the configurations of the upcoming integrated solutions. Intel is to double and then quadruple the GPU core count over Alder Lake iGPU solution.

• MTL_3x4x16= 192 (Execution Units)
• ARL_6x4x16= 384 (Execution Units)

https://videocardz.com/newz/intel-a...sti-dgpu-raptor-meteor-arrow-lunar-lake-igpus

 

[Nemesis11]

Mas acho que 80mm2 é apenas o GPU

Sim, o menor que 80 mm2 é o "Chiplet" do GPU.

Será isso o mega APU que andamos a conversar? 320 EU?!?

Pode-se chamar "Mega APU" a um APU que tem um GPU menor de 80 mm2?
320 ou 384 EUs é mais do triplo de EUs que os Alder Lake para portáteis tem (96 EUs, se não estou em erro) e é um valor muito interessante nos dias de hoje. No entanto, daqui a 2 anos, 320 ou 384 EUs será um valor elevado para um APU?
A meu ver, um "Mega APU" é um APU que tem um GPU que compete com Gráficas dedicadas Mid-End, pelo menos. Não estou a ver que seja isto. <80 mm2 é mais pequeno que a 6500XT, por exemplo.

 

[Dark Kaeser]

Bem espremido é só caroços... mas, apesar de já ter sido objecto de outro artigo

Interview with Intel’s Raja Koduri: Zettascale or ZettaFLOP? Metaverse what?​

IC: You’ve spoken about this 1000x jump in performance, and with Patrick you labeled it as an architecture jump of 16x, power and thermals are 2x, data movement is 3x, and process is 5x. That is about 500x, on top of the two ExaFLOP Aurora system, gets to a ZettaFLOP.

Just going through some of the specific numbers - the 16x for architecture is the biggest contribution to that. Should we think of that in pure IPC improvements, or are we talking about a full spectrum of improvements combined with the paradigm shifts, such as processing and memory and that sort of thing?

RK: A combination of both I'd say. The foundational element is the IPC per watt improvement. We know how to do 16x performance improvement pretty easily, or relatively. But doing it without burning the power is the challenge there in terms of both the architecture and microarchitectural opportunities that are ahead of us.

IC: On the power and thermal side, you mentioned 2x, which is the lowest multiplier. You meant the ability to use both a lower voltage and better cooling, although I immediately heard it and thought we're going to start getting 800 to 1000 watt GPUs! But this sounds more around better power management, how to architect the power, and the ability to have the process for thermal packaging and voltages. That also moves into how architecture is done, as well as some of the others on this list, such as packaging and integration. Some of these multipliers overlap, significantly, so isn’t it hard to tell them apart in that way?

RK: Some of them have opportunities beyond those numbers. For example, when we say ‘power and thermals’, it's also power delivery - if you just look at the way we build computers today, just the regulated losses that you have on how we deliver current to the chip. With integration at a system scale, there are opportunities - not just Intel identified opportunities, but many folks outside Intel have called things out, such as driving higher voltages [in the backplane] to drive lower current in. So there are opportunities there. The data center folks have been taking advantage of some of this stuff already, as well as the big hyperscalers - but there is more available with integration.

But you said something very interesting - if we viewed Zettascale as a collection of components, such as GPUs, CPUs, and memories and all - each of them are fed separate power. You could have a 300 watt GPU and a 250 watt CPU. That's one way of doing the math. But if I have X amount of compute, what amount of current is needed to deliver to that compute - there are large power losses today because each component has its own separate power delivery mechanisms, so we waste a lot of energy.

The key idea behind all of this stuff is the ‘unit of compute’. Today, when I say ‘unit of compute’, we mean that a CPU is a unit of compute, or a single GPU is a unit of compute. There is no reason why they have to be that way. That's what we define today for market reasons, for product reasons and all that stuff, but what if your new ‘unit of compute’ is something different? Each unit of compute has a particular overhead - beyond the core compute, it’s about delivering power to a thermal solution. There’s cost too, right? There bunch of materials on the board and all the repetitive components could potentially be combined for lower overall losses.

Historically, this is one of the foundations of Moore's Law. Integration with Integration. We drove this extraordinary foundation, and now we have a supercomputer in your pocket in a phone. No reason that aspect of Moore's law needs to stop, because there's still an opportunity just even beyond transistors. Just the integration - integration can drive some order of magnitude efficiencies.

https://www.anandtech.com/show/1729...koduri-zettascale-or-zettaflop-metaverse-what

É impressão minha ou ele acabou de descrever o Falcon Shores a.k.a "Super APU".

 

[Nemesis11]

Na entrevista toda, vai além do Falcon Shores. O Falcon Shores é "apenas" uma fase. Acho que esta parte da entrevista resume bem o que a Intel pretende:

IC: I wanted to go through some of the timescales for Zettaverse. You’ve already been through them with Patrick Kennedy from ServeTheHome – it’s annoying because I asked for this interview before you bumped into him at Supercomputing and had this chat! But to build on what was published there - in that interview, you said Zettascale had three phases. First is optimizing Exascale with Next-Gen Xeon and Next-Gen GPU in 2022/2023; the second phase is in 2024/2025 with the integration of Xeon plus Xe called Falcon as well as Silicon Photonics or ‘LightBringer’; then a third phase simply labeled Zettascale because it's 4 to 5 years away, and Intel doesn't talk about things that far out. It sounds to me like you're aligning these phases with specific products and introductions into the market?

RK: Definitely. With phase one and phase two, we have more clarity on the products. But phase three is about our technology roadmap. When I use the word technology, by the way, just for your audience and readers, it is things that take a long time. It means process technologies, or a new packaging technology, or the next generation of silicon photonics - those take a long time. The products align to things like Sapphire Rapids, like Alchemist or BattleMage, where we pack these technologies into a particular architect system architecture.

A ideia é ter vários avanços em várias áreas, em paralelo.
Além dos avanços a nível de performance, parece-me que a estratégia da Intel também passa muito por flexibilizar as ofertas que têm. Uma espécie de "Lego", em que conseguem oferecer soluções em pouco tempo, adaptadas às necessidades de cada Cliente.
Por exemplo, um Cliente grande pode querer 1 Chip CPU, 3 Chips GPUs, X Lanes Pci-Ex, Y capacidade de memória com Z Bandwidth, etc e outro Cliente Grande, pode criar um produto bastante diferente, usando alguns destes mesmos Chips e podendo colocar outros.

 

[Dark Kaeser]

Sim, mas esse "roadmap" ja ele tinha falado com o Patrick do servethehome, ainda em modo "manual"

https://www.servethehome.com/rajas-chip-notes-lay-out-intels-path-to-zettascale/

Depois isso aparece durante a apresentação dos roadmaps de há um mês.

Apenas salientei essa parte, porque no fundo entrou em mais pormenor.

 

[Dark Kaeser]

https://twitter.com/i/web/status/1503719118784053262