Processador Risc-V

[Dark Kaeser]

SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions​

The SiFive Performance P470 and P670 share the following features:

• Full RISC-V RVA22 profile compliance
• Full, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification
• RISC-V Vector Cryptography extensions
• SiFive WorldGuard system security
• Support for virtualization, including a separate IOMMU for accelerating virtualized device IO
• Advanced Interrupt Architecture (AIA) compliant interrupt controller with better support for Message Signal Interrupts (MSI) and virtualization
• Enhanced scalability with fully coherent multi-core, multi-cluster, with support for up to 16 cores

SiFive Performance P670​

The SiFive Performance P670 core is comparable to the Arm Cortex-A78, can achieve a frequency of up to 3.4 GHz when manufactured with a 5nm process, delivers a performance of more than 12 SpecINT2k6/GHz, as well as higher single thread performance and twice the compute density compared to “legacy solution” (aka Cortex-A78), and embeds two 128-bit Vector ALUs compliant with the ratified RISC-V Vector v1.0 specification. It will be found in premium wearables, networking, robotics, and mobile SoCs, and is an upgrade to the SiFive Performance P650, which lacks the Vector Extensions.

SiFive Performance P470​

The SiFive Performance P470 core will compete against the Arm Cortex-A55 core, yet it is said to also achieve up to 3.4GHz with a 5nm process. It also offers 8+ SpecINT2k6/GHz within a small area and power envelope, as well as four times the compute density of”a leading competitor” also known as Cortex-A55… While the P670 includes two 128-bit RISC-V Vector ALU, the P470 embeds only one. SiFive will also release the P450 with the similar specifications as the P470 minus the Vector Unit.

https://www.cnx-software.com/2022/1...sc-v-processors-add-risc-v-vector-extensions/

SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores ​

A new significant feature that comes with the P670 is support for the RISC-V Vector 1.0 specification. The P670 integrates two 128-bit vector units. It’s worth noting that SiFive also offers a trimmed-down version of the P670 called the P650 which simply excludes the vector units for customers that do not require the additional vector capabilities or for customers that are more area constrained.

The P470 achieves this by inheriting much of the P550 design but optimizing for power efficiency and area. The result is a high-performance core – comparable in performance to the P550 – but at nearly one-fourth the area of the P670.

Like the P670, the P470 comes with support for the RISC-V Vector 1.0 specification. It comes with a single 128-bit vector unit. There is also a vector-less version, the P450 – which excludes the vector unit for extremely area-constrained customers.

https://fuse.wikichip.org/news/7318...s-line-into-performance-and-efficiency-cores/

 

[Nemesis11]

Acho que é o primeiro anuncio concreto de um processador Risc-V para o mercado servidores "tradicional".
Ventana Veyron V1 (Nome curioso )

Configuração máxima de 12 Chiplets (5 nm) com 16 Cores cada @ 3.6 Ghz + IO die (12 ou 16 nm). 64 KB L1, 1 MB L2 por Core, 48 MB L3 por Chiplet (576 MB no Total). Samples em Q2 ou Q3 2023.
Os Chiplets podem ter 6, 8, 12 e 16 Cores cada.
Se bem percebo o slide, esperam um TDP de 280W na versão 128 Cores, com um pouco melhor performance que o AMD Epyc 7763.

https://www.forbes.com/sites/karlfr...s-risc-v-cpu-challenging-arm/?sh=397077d57e10
https://www.hpcwire.com/2022/12/13/ventana-plans-to-bring-risc-v-chip-to-hpc/

Algo que acho curioso. Eles têm um acordo com a Intel, a nível de Foundry, mas pelo que percebo, este 5 nm são da TSMC.

https://www.forbes.com/sites/patric...res-with-ventana-micro-systems-compute-tiles/

 

[Dark Kaeser]

8 wide?!

Querem concorrer com os IBM Z

 

[Dark Kaeser]

Sipeed LM4A – T-Head TH1520 RISC-V module to power Raspberry Pi 4 competitor and cluster board​

Sipeed LM4A specifications:

• SoC – ***** T-Head TH1520 quad-core RISC-V Xuantie C910 (RV64GCV) processor @ 2.5 GHz, Xuantie C906 audio DSP @ 800 MHz, low power Xuantie E902 core, 50 GFLOPS Imagination 3D GPU, and 4 TOPS NPU
• System Memory – 4GB, 8GB, or 16GB RAM
• Storage – Optional eMMC flash with 16GB, 32GB, or 64 GB capacity
• Networking – Up to 2x Gigabit Ethernet PHY
• Host interface – 260-pin SO-DIMM connector
• Dimensions – 69 x 45mm

Sipeed shared a photo of a cluster board with seven LM4A RISC-V system-on-module each with a USB 3.0 port, and I can see what looks like a few RJ45 ports on the back as well as on one HDMI output.

https://www.cnx-software.com/2022/1...-raspberry-pi-4-competitor-and-cluster-board/

 

[Dark Kaeser]

Lichee Pi 4A RISC-V SBC takes on Raspberry Pi 4 with TH1520 processor​

Lichee Pi 4A is a single board computer (SBC) powered by ***** T-Head TH1520 quad-core RISC-V Xuantie C910 processor @ 1.8 GHz with an Imagination GPU and a 4 TOPS NPU for AI that can compete against the Raspberry Pi 4 in terms of performance and features.

The TH1520 used to be advertised at up to 2.5 GHz, but it seems to have now come down to 1.8 GHz. Software support will include Debian, OpenWrt, and Android in Q1 2023, and more operating systems should be supported as time passes by. Here are again some benchmarks that were shared in the initial announcement about the LM4A module.

The company had already showcased a 7-module cluster board based on LM4A at the time of the first announcement, but they will also release the Lichee Router 4A based on the Lichee Pi 4A SBC, a 6-inch Lichee Phone 4A and a 10.1-inch Lichee Pad 4A all fitted with the LM4A module.

We do get some pricing guidelines on Twitter, as Sipeed says the Lichee Pi 4A 8GB RAM will go for about $99, and the 16GB RAM model for around $140.

https://www.cnx-software.com/2022/12/27/lichee-pi-4a-risc-v-sbc-raspberry-pi-4-th1520-processor/

 

[muddymind]

https://arstechnica.com/gadgets/2023/01/google-announces-official-android-support-for-risc-v/

A ARM ainda se vai lixar com os atritos actuais.

 

[Dark Kaeser]

Pendei que tinha colocado, mas afinal esqueci-me, um pequeno resumo e falta aí muita coisa

RISC-V Summit 2022: All Your CPUs Belong to Us​

Redmond’s reason for saying that RISC-V is inevitable is that its growth and success are built upon shared investments of many companies, universities and contributors. RISC-V International has more than 3180 members. Billions of dollars have been invested in the architecture, including national programs from countries and regions such as India and the E.U. This enables the development of the “best” processor in multiple price and performance categories with the contributions of so many ideas and collective knowledge. Because RISC-V is scalable, customizable and modular, it can easily be optimized for different workloads and applications.

Markets pulling for RISC-V​

One of the most talked about markets was automotive with auto-grade cores from Andes, MIPS, NSI-TEXE (Denso) and others. One estimate that Redmond quoted in her keynote is that RISC-V would be in 10% of new automobiles by 2025.

For data center applications, there are products from *****, Esperanto.ai and Ventana.

Ventana Veyron V1​

In what was probably the biggest hardware news at the RISC-V Summit, Ventana revealed details of its new Veyron V1 data center class chiplet processor. This 8-wide superscalar, out-of-order CPU design with RAS (reliability, availability and serviceability) features running at 3.6GHz is designed to go head-to-head with the latest server processors from shoppingmode AMD, Arm and Intel.


The chiplet is fabricated in TSMC’s 5-nm process with 48MB of L3 cache per 16-CPU cluster. By combining multiple Veyron V1 chiplets with a central memory and I/O chip, a silicon vendor or systems company can build a server processor with 128 CPU cores in a socket.

MIPS​

While we know from last year that the restructured MIPS was adopting RISC-V for future CPU development, at the Summit the company announced that Mobileye adopted it eVocore P8700 for the next-generation EyeQ SoC for autonomous driving and advanced driver assistance systems (ADAS). Mobileye had been using the MIPS architecture for its existing products. The P8700 is a multi-threaded, multi-core, multi-cluster design that can scale to 64 clusters, 512 cores and 1,024 threads.

SiFive​

SiFive CEO Patrick Little gave an update on the company’s progress over the year. One milestone of note was the collaboration with MicroChip in winning the Jet Propulsion Lab (JPL)/NASA design for the next generation of space-capable computers called the HPSC. (There was also a talk about the HPSC from a JPL representative at the conference.)

Andes​

One of the earliest CPU IP providers to embrace RISC-V was Andes. The company has been steadily building a selection of CPU cores from the low end and is now adding vector extensions. Andes announced a new high end CPU core called the AX65, with a 13-stage pipeline and out-of-order execution. The smaller NX45V and AX45MPV core offer vector and scalar operation. A big win for the company is the Renesas RZ/Five MPU for automotive. Andes already offers cores that are compliant to ISO26262 and ASIL-B safety standards. While the company can’t reveal all its customer projects, it did say it has a 5-nm project in production with a 3-nm design due in 2024.

The CTO of RISC-V International, Mark Himelstein, recognized the challenges and said that software ecosystem development was his No. 1 priority.

https://www.eetimes.com/risc-v-summit-2022-all-your-cpus-belong-to-us/

 

[Nemesis11]

https://arstechnica.com/gadgets/2023/01/google-announces-official-android-support-for-risc-v/

A ARM ainda se vai lixar com os atritos actuais.

Esta noticia é super importante para Risc-V.

Pendei que tinha colocado, mas afinal esqueci-me, um pequeno resumo e falta aí muita coisa

RISC-V Summit 2022: All Your CPUs Belong to Us​

Playlist da Conferência:
https://www.youtube.com/playlist?list=PL85jopFZCnbPPRyjl_qMQ50DPq_iQKhFg

Pelo meio, a Intel deu mais detalhes da Board Micro-ATX "Horse Creek", com o SOC da Intel, usando os Cores P550 da SiFive:

Here’s what that looks like:

• Intel 4 Process
• 4mm x 4mm monolithic die
• 19x19 standard FBGA package
• Intel DDR5-5600 Hard IP PhV
• interfaced with Cadence* DDR5
• Controller IP
• Intel PCIe* Gen5 Hard IP PhV interfaced with Synopsys* PCle*
• Controller IP - supports 8 lanes
• 2 MB Shared Scratchpad memory
• Other common SoC peripheral support

https://community.intel.com/t5/Blog...-latest-RISC-V-development-board/post/1448348

 

[JPgod]

Enrretanto a Intel saiu do barco do RISC-V

https://twitter.com/i/web/status/1618655414614372352

 

[Dark Kaeser]

Ainda não é "o abandono", até porque este programa na realidade cinge-se à implementação da ISA em FPGA para "desenvolvimento".

https://www.edn.com/four-things-to-know-about-the-intel-pathfinder-for-risc-v/

Mas olhando para as contas da Intel...

 

[Nemesis11]

The program began in August 2022 and was meant to help accelerate the development of RISC-V chips through a unified integrated development environment (IDE) using industry-standard toolchains. The tools allowed users to build RISC-V chips and then run them on an FPGA. Many of the large RISC-V companies, not to mention RISC-V International, supported the program.

Intel also has many other RISC-V initiatives underway. Intel and SiFive just jointly announced the HiFive Pro P550 RISC-V development board a mere three days ago, and it is scheduled to be available this summer.

The sudden termination of the Intel Pathfinder for RISC-V program, not to mention Gelsinger's comments that Intel is also looking for other cost-cutting targets across the company, calls into question Intel's other new investments in the RISC-V ecosystem.

https://www.tomshardware.com/news/intel-sunsets-network-switch-biz-kills-risc-v-pathfinder-program

A Intel tem que perceber uma coisa. Se começam a ter um histórico, na criação e cancelamento de produtos em pouco tempo, uma boa parte dos clientes nunca irá apostar em novos produtos da Intel, com medo de serem cancelados. Se os produtos não ganharem tracção por causa desse medo, a Intel vê-se obrigada a cancelar os produtos, criando assim um ciclo vicioso.
Pergunto, depois deste cancelamento, quem irá ter confiança em apostar na Dev Board com um SOC Risc-V da Intel?

 

[Nemesis11]

Mais uma iniciativa Risc-V para o mercado de servidores. Desta vez vem da China. A empresa tem o nome de Sophgo e o modelo SG2042.

https://docs.google.com/presentation/d/1DIl2rzje2C1mKaxm4a5iLBuzHb10LqWV5YDNcEtUrpg

Parece-me muito cedo para Risc-V neste mercado, mas é interessante haver mais que uma iniciativa.
Este CPU é mais tradicional e menos ambicioso que o da Ventana.

 

[Nemesis11]

SBC Asus Tinker V:

It’s not a particularly powerful RISC-V chip. At the heart of the Tinker V is a Renesas RZ/Five processor with a 1 GHz Andes AX45MP single-core RISC-V processor.

Ports include:

• 2 x GbE Ethernet
• 1 x micro USB
• 1 x micro USB (OTG)
• 2 x CAN Bus (6-pin terminal block)
• 2 x COM RS-232 (5-pin terminal block)

There’s also a 20-pin GPIO header and JTAG debug pin header and a DC power input jack.

Asus says the board support Debian and Yocto Linux operating systems.

There’s no word on pricing or availability yet, but Asus is showing off the Tinker V, as well as other IoT products, at the Embedded World show in Germany this week.

https://liliputing.com/asus-tinker-v-is-the-companys-first-single-board-pc-with-a-risc-v-chip/
https://tinker-board.asus.com/product/tinker-v.html
https://www.renesas.com/us/en/produ...des-ax45mp-single-10-ghz-2ch-gigabit-ethernet

Dependendo do preço, pode ser interessante.

 

[Dark Kaeser]

Tenstorrent Shares Roadmap of Ultra-High-Performance RISC-V CPUs and AI Accelerators​

One Microarchitecture, Five CPU IPs in One Year​

Tenstorrent now has five different RISC-V CPU core IPs — with two-wide, three-wide, four-wide, six-wide, and eight-wide decoding — to use in its own processors or license to interested parties. For those potential customers who need a very basic CPU, the company can offer small cores with two-wide execution, but for those who need higher performance for edge, client PCs, and high-performance computing, it has six-wide Alastor and eight-wide Ascalon cores.

Each out-of-order Ascalon (RV64ACDHFMV) core with eight-wide decode has six ALUs, two FPUs, and two 256-bit vector units, making it quite beefy. Considering that modern x86 designs use four-wide (Zen 4) or six-wide (Golden Cove) decoders, we are looking at a very capable core.

In addition to a variety of RISC-V general-purpose cores, Tenstorrent has its proprietary Tensix cores tailored for neural network inference and training. Each Tensix core comprises of five RISC cores, an array math unit for tensor operations, a SIMD unit for vector operations, 1MB or 2MB of SRAM, and fixed function hardware for accelerating network packet operations and compression/decompression. Tensix cores support a variety of data formats, including BF4, BF8, INT8, FP16, BF16, and even FP64.

Impressive Roadmap​

Right now, Tenstorrent has two products: a machine learning processor called Grayskull that offers performance of around 315 INT8 TOPS that plugs into a PCIe Gen4 slot, as well as a networked Wormhole ML processor with approximately 350 INT8 TOPS of performance and uses a GDDR6 memory subsystem, a PCIe Gen4 x16 interface and has a 400GbE connection to other machines.

Both devices require a host CPU and are available as add-in-boards as well as inside pre-built Tenstorrent servers. One 4U Nebula server containing 32 Wormhole ML cards offers around 12 INT8 POPS of performance at 6kW.

Later this year, the company plans to tape out its first standalone CPU+ML solution — Black Hole — that combines 24 SiFive X280 RISC-V cores and a multitude of 3rd Generation Tensix cores interconnected using two 2D torus networks running in opposite directions for machine learning workloads. The device will offer 1 INT8 POPS of compute throughput (approximately three times performance uplift compared to its predecessor), eight channels of GDDR6 memory, 1200 Gb/s Ethernet connectivity, and PCIe Gen5 lanes.

https://www.tomshardware.com/news/t...flow&utm_source=twitter.com&utm_medium=social

 

[Nemesis11]

Pelo que percebo, na parte do Processador, o cluster mais pequeno é constituído por 8 Cores Escalon + 12 MB LLC:

Que depois ficam num Cluster maior com 32 Cores, que por sua vez, num Chiplet, existem 4 destes Clusters (128 Cores no total). O nome do Chiplet é Aegis.

O complexo total com os processadores pode ter mais que 1 chiplet.

https://tenstorrent.com/risc-v/

Além do Chiplet CPUs, há Chiplets de ML, IO e Memória.

Bastante interessante.

 

[Dark Kaeser]

Building High-Performance RISC-V Cores for Everything @Ian Cutress​

 

[Dark Kaeser]

https://twitter.com/i/web/status/1655914204510011392

O post tem um erro, não é 10w total, é 10w para cada chiplet Occamy, e o SoC tem 2x Occamy e ainda 2x HBM2e, e isto a 12nm GF LPP

Auf der DATE-Konferenz (Design, Automation and Test in Europe) haben die Entwickler von der ETH Zürich sowie der Universität von Bologna zusammen mit den beteiligten Unternehmen, bzw. Plattform-Entwicklern wie PULP (Parallel Ultra-Low Power), GlobalFoundries, Rambus, Micron, Synopsys und Avery den Occamy vorgestellt, einen HPC-Chip mit Chiplet-Design und insgesamt 432 RISC-V-Kernen.

https://www.hardwareluxx.de/index.p...e-effizienter-number-cruncher-aus-europa.html

 

[Dark Kaeser]

Meta Platforms Crafts Homegrown AI Inference Chip, AI Training Next​

We will be drilling down into all of this content over the next several days, as well as doing a Q&A with Alexis Black Bjorlin, vice president of infrastructure at Meta Platforms and one of the key executives added to the custom silicon team at the company a year ago. But for now, we are going to focus on the Meta Training and Inference Accelerator, or MTIA v1 for short.

Joel Coburn, a software engineer at Meta Platforms, showed this chart as part of the AI Infra @ Scale event that illustrates how the DLRM inference models at the company have been growing in size and computational demand in the past three years and how the company expects them to grow in the next eighteen months:

Banking On RISC-V For MTIA​

Facebook has historically been strong proponents of open source software and hardware, and it would have been a big surprise if Meta Platforms did not embrace a RISC-V architecture for the MTIA accelerator. It is, of course, based on a dual-core RISC-V processing element, wrapped with a whole bunch of stuff but not so much that it won’t fit into a 25 watt chip and a 35 watt dual M.2 peripheral card.

Here are the basic specs of the MTIA v1 chip:

The MTIA v1 inference chip has a grid of 64 processing elements that have 128 MB of SRAM memory wrapped around them that can be used as primary storage or for cache memory that front ends sixteen low power DDR5 (LPDDR5) memory controllers. This LPDDR5 memory is used in laptops and is also being used in Nvidia’s impending Grace Arm server CPU. Those sixteen channels of LPDDR5 memory can provide up to 64 GB of external memory, suitable for holding those big fat embeddings that are necessary for DLRMs. (More on that in a moment.)

Those 64 processing elements are based on a pair of RISC-V cores, one plain vanilla and the other with vector math extensions. Each processing element has 128 KB of local memory and fixed function units to do FP16 and INT8 math, crank through non-linear functions, and move data.

Here is what the MTIA v1 board looks like:

https://www.nextplatform.com/2023/0...homegrown-ai-inference-chip-ai-training-next/

 

[Nemesis11]

Tenho a SBC Visionfive 2 há uns tempos, mas usei-a pouco até agora. Fica aqui apenas umas fotos e umas impressões muito iniciais.

A nível do funcionamento do hardware, sem ser o GPU, parece-me que o principal funciona ok. Vi uns erros e comportamentos "estranhos" no Wireless, mas nada de especial.
A nível do software, o estado diria que é "alpha". Dá um pouco mais trabalho que uma SBC normal, por exemplo a fazer o update da ROM, há software que não arranca, ou dá erros, ou crasha ou simplesmente, ainda não está nos repositórios. Além disso, a nível de performance, é "inconsistente". Há software que parece estar mais "polido" que outro.
Era o que estava à espera.

Mais algumas pequenas notas:

• Aquela placa USB é o Wireless. Não está integrado na placa.
• Desliguei a ventoinha, porque mesmo em load, o dissipador parece-me suficiente.
• Só ainda usei MicroSD como storage. Ainda não experimentei storage pelos conectores M.2 ou eMMC.

 

[muddymind]

https://www.prnewswire.com/news-rel...pen-source-software-for-risc-v-301838005.html