GlobalFoundries 14 nm LPP FinFET Node Taped Out, Yields Good

[V3ctor]

GlobalFoundries 14 nm LPP FinFET Node Taped Out, Yields Good


Excelentes noticias!!

 

[muddymind]

Com as notícias que a AMD vai fabricar o ZEN na TSMC não sei até que ponto conseguirão ter um processo LPE ou equivalente...

 

[Dark Kaeser]

Até ver não existem notícias nenhumas relativamente ao ZEN ser fabricado na TSMC ou na GF, apenas rumores.

O WC...Tech limitou-se a reproduzir algo que viu no EXPReview (chinês ou coisa parecida), que por sua vez reproduziu algo que é uma opinião num site italiano bitsandchips.

Certo só as declarações do CEO da GF, Sanjay Jha, há umas semanas na China:

Jha: You’re right. We’ve been a quarter or two late on the leading-edge nodes. That’s one of the issues we’ve been trying to address. Today, we have one 14nm customer ramping to volume right now, followed by two others who will be ramping later this year and early next year. That’s not too bad. When it comes to 14nm volume production, I think we are roughly on par with our competitors.

http://www.eetimes.com/document.asp?doc_id=1327709&page_number=2

que mesmo assim apenas menciona 3 clientes, mas sem referir quais.

 

[Gaugamela]

Fui eu que coloquei o link de que iam usar o processo da TSMC. Se usarem o 14nm LPP são boas notícias porque esse já deve ser um 14nm Finfet "puro". O LPE é um híbrido de 20nm e 14nm. Vamos esperar por desenvolvimentos.

 

[Dark Kaeser]

Eu até acho que ambos usam 14nm ou 16nm no FEOL, e 20nm no BEOL, pelo menos no anúncio inicial quer a TSMC quer a GF o disseram porque iam portar dos 20nm, e usar a mesma BEOL, Mas a GF cancelou os 20nm e como tal os 14xm, agora os 14nm da Samsung não me recordo.

http://www.anandtech.com/show/8223/...miconductor-physics-technology-and-industry/3

 

[Gaugamela]

A única análise feita nesse sentido era do 14nm LPE que vem da Samsung.
O LPP ainda não foi analisado, mas como falam de melhorias em poder e consumo face ao 14nm LPE não me admirava que fosse 14nm por inteiro.

 

[Dark Kaeser]

GlobalFoundries 14nm Process Update

The 14LPE process was the first generation and was qualified in January. A second generation 14LPP process was qualified in September. They are now shipping 14nm parts to customers.
...
Production qualification is greater than 60% yield on a 128Mb SRAM. Yields on LPP are >20 points higher than that now (>80%) and LPE is ahead of that.

https://www.semiwiki.com/forum/content/5119-globalfoundries-14nm-process-update.html

 

[Gaugamela]

O LPP então vai ser um híbrido de 14nm/20nm, apenas mais eficiente que o LPE.

 

[Dark Kaeser]

Press Releases
GLOBALFOUNDRIES Achieves 14nm FinFET Technology Success for Next-Generation AMD Products

AMD has taped out multiple products using GLOBALFOUNDRIES’ 14nm Low Power Plus (14LPP) process technology and is currently conducting validation work on 14LPP production samples. Today’s announcement represents another significant milestone towards reaching full production readiness of GLOBALFOUNDRIES’ 14LPP process technology, which will reach high-volume production in 2016.

http://www.globalfoundries.com/news...logy-success-for-next-generation-amd-products

 

[Gaugamela]

Boas notícias.
Vamos ver se é Zen ou GPUs ou ambos.

 

[Dark Kaeser]

GLOBALFOUNDRIES Expands to Meet Worldwide Customer Demand
Company invests for capacity growth in the United States, Germany, China and Singapore

GF plans to expand 14nm FinFET capacity by an additional 20 percent at its Fab 8 facility in New York, with the new production capabilities to come online in the beginning of 2018.

http://www.globalfoundries.com/news...ies-expands-to-meet-worldwide-customer-demand

 

[Dark Kaeser]

Para não estar a abrir novo tópico.
Relativamente à situação do fornecimento de chips para contratos com o Departamento de Defesa Norte Americano.

-
DoD Microelectronics Office Boosts Contract Ceiling

The Defense Microelectronics Activity, a branch of DoD’s laboratory network, last week awarded a $10.27 billion contract modification to eight vendors under a streamlined technology acquisition program. The award boosts the total for electronics engineering and manufacturing under the Advanced Technology Support Program (ATSP) to as much as $17.47 billion.

Vendors include some of the largest U.S. military contractors: Boeing, General Dynamics, Honeywell, Lockheed Martin, Northrop Grumman Systems and Raytheon Co.

GlobalFoundries serves as the office’s trusted foundry under a contract that extends through September 2023.

https://www.eetimes.com/dod-microel...?utm_source=eetimes&utm_medium=relatedcontent

- Trusted DoD Fabs GloFlo, SkyWater Join Forces

The foundry agreement follows a $170 million DoD contract award to SkyWater last October that funds a multi-phase project to manufacture radiation-hardened chips for military and aerospace customers. The initial $80 million phase includes development of a 90-nm rad-hard electronics manufacturing capability.

https://www.eetimes.com/trusted-dod-fabs-gloflo-skywater-join-forces/

 

[Nemesis11]

É uma decisão politica, mas tratando-se de contratos militares, é perfeitamente compreensivel. A GloFo tem uma das fábricas em NY (Antiga fábrica IBM).

 

[Dark Kaeser]

GLOBALFOUNDRIES to Acquire Land in Malta, NY, Positioning its Advanced Manufacturing Facility for Future Growth

The land parcel is located at the southeast end of the New York State Energy Research and Development Authority (NYSERDA) Saratoga Technology + Energy Park (STEP) campus, adjacent to Stonebreak Road Extension, between GF’s Fab 8 facility and Hermes Road. Exercising the option to purchase the land and commencement of development to expand GF’s Fab 8 facility will be subject to zoning regulations and client demand.

https://www.globalfoundries.com/new...cquire-land-malta-ny-positioning-its-advanced
e entretanto uma nova variante, da já de si variante... (assim uma espécie de 14nm +++ )

Optimized for AI Accelerator Applications, GLOBALFOUNDRIES 12LP+ FinFET Solution Ready for Production

12LP+ builds upon GF’s established 14nm/12LP platform, of which GF has shipped more than one million wafers.

Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling. These advancements are achieved in 12LP+ through its next-generation standard cell library with performance-driven area optimized components, single Fin cells, a new low-voltage SRAM bitcell, and improved analog layout design rules.

12LP+, a specialized application solution, is augmented by GF’s AI design reference package, as well as GF’s co-development, packaging, and post-fab turnkey services – which together enable a holistic experience for designing low-power, cost-effective circuits optimized for AI applications.

In addition to 12LP’s existing IP portfolio, GF will expand the IP validations for 12LP+ to include PCIe 3/4/5 and USB 2/3 to host processors, HBM2/2e, DDR/LPDDR4/4x and GDDR6 to external memory, and chip-to-chip interconnect for designers and clients pursuing chiplet architectures.

https://www.globalfoundries.com/new...ator-applications-globalfoundries-12lp-finfet

Aparentemente a grande novidade é a introdução de interposers 2.5D, que permitirá o fabrico de chiplets, a notícia da aquisição do terreno ao lado da Fab8 (14/12nm) é que é a grande surpresa depois da venda da Fab3E (Singapura) à VIS, e das Fab10 (ex-IBM acho que também vai até aos 14nm provavelmente a HP SOI da própria IBM) à ON Semi e da Fab9 (ex-IBM 90nm) à Toppan, já nem sei qual destas 2 é que era uma das "trusted foundry" para contratos militares.

Até porque mais mês menos mês, a AMD deixará livre quase toda a capacidade a 14nm.
Só o fabrico do IO para os Ryzen, alguns APU mais antigos e algumas GPU não deve absorver toda a capacidade actual, e quando até isso sair de lá, vão encher com o quê?

 

[miguelbazil]

Wait, eles vêm para a Europa para produzir? Percebi bem?

 

[JAFoNEXUS]

Wait, eles vêm para a Europa para produzir? Percebi bem?

Malta, NY !

 

[Dark Kaeser]

Sim, Malta NY, na Europa já eles produzem, na "Silicon Saxony", Desden.

Mas no caso eles exerceram o direito de preferência sobre um terreno anexo, mas só faz sentido a aquisição do terreno para expansão da Fab8.
Não sei como está a história da FDSoi, eles supostamente eram para usar um processo 12FDX, não sei se é suposto ser planar (ou seja nada de FinFet) e usando wafers especiais.

Para o tal investimento em chips militares isto é mais relevante que os 7nm. E o timing também é capaz de não ser coincidência. Digo eu.

 

[vandaminator]

Vão começar a produzir Ram.

 

[Dark Kaeser]

Dram?

Acho que a única coisa relacionada com memória que eles produzem é MRam e é IP de 3°, neste caso a Everspin.
https://www.anandtech.com/show/15617/globalfoundries-everspin-extend-mram-pact-to-12nm

 

[Dark Kaeser]

Relacionado com o post #14 e o anúncio dos 12LP+

Há cerca de 2 anos a GF e a ARM tinham anunciado um projecto de 3D stacking

Aug 7, 2019

GLOBALFOUNDRIES and Arm Demonstrate High-Density 3D Stack Test Chip for High Performance Compute Applications​

https://globalfoundries.com/press-r...h-density-3d-stack-test-chip-high-performance

um post de há uns meses

3D stacking for next-generation high performance energy efficient systems​

After a few years of conducting simulation-based explorations into 3D-ICs, Arm Research decided that these questions could best be answered by building a demonstrator. This required a strong collaboration between design, electronic design automation (EDA), and manufacturing.

To make that demonstrator a reality, Arm partnered with GLOBALFOUNDRIES to tape-out a 3D prototype design in 2019. Named Project Trishul, the goal was to demonstrate the feasibility and readiness of high-density, face-to-face, wafer-bonded 3D stacking technologies for high performance, energy-efficient designs. Figure 1 shows the piece of a representative Arm Neoverse® system the team investigated, and a block diagram of the subsystem components that were demonstrated in 3D. We are happy to announce that the 3D hybrid-bonded chips are back from fabrication, and we have run comprehensive tests to measure and characterize them.

Figure 1: Arm Neoverse CMN-600 and a 2x2 mesh implemented in 3D. Only the "XP" blocks (NoC mesh router) blocks in blue and white are implemented in the test-vehicle.

Figure 2: (a) Top and bottom die GDS view (b) zoom-in view showing I/O cell connected to top-metal peripheral pads for pre-bond testing and back-side C4 bumps using Through-Silicon-Via (TSV) for post-bond 3D tests (c) C4 bumps, TSV and wafer-bond pads top-view (d) cross-sectional schematic view and (e) corresponding die cross-section from the 3D test-vehicle.

The key learning that we validated from this 3D test-vehicle was that, from an electrical-connectivity perspective, face-to-face hybrid bonding technology does not introduce any significant delay penalty. If the cross-die process skew can be managed, a single clock domain synchronous design with an order of magnitude higher bandwidth and lower energy, compared to state-of-the-art bump-based die stacking techniques, can be implemented. 3D stacking can significantly improve on-chip memory capacity and bandwidth, and can also improve the overall throughput of the system, all while potentially reducing costs.

https://community.arm.com/developer...ion-high-performance-energy-efficient-systems