45nm Era Starts Now!!

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Podes sempre esperar pelo QX9770 mas esse é mais caro por apenas um bump de speed e parece gastar mais que o QX9650
 
Já não vejo a hora de serem comercializados os Q9450...
Este levou-me a mudar de ideias em relação ao Q6600, apesar de ser provisório este CPU que tenho actualmente até aleija, tá a limitar-me o sistema que é uma coisa parva...
 
será que sou o unico a não achar piada a coolers com leds? principalmente stock coolers.

Quem usa stock cooler tem uma caixa totalmente fechada por isso não lhe faz diferença.

Quem compra caixas com acrílicos normalmente nunca deixa o stock.

É a intel a tornar-se uma thermaltake wannabe.
 
Intel divulges 45nm process details...

David Lammers, News Editor -- Semiconductor International, 12/12/2007 5:39:00 AM

Intel Corp. (Santa Clara, Calif.) provided some details of its 45 nm high-k/metal gate (HKMG) process flow at the International Electron Devices Meeting (IEDM) in Washington, D.C., although key elements of the pFET electrode metal remained shrouded.

Kaizad Mistry, vice president of logic integration, said Intel used a "high-k first, metal gate last" approach. By keeping the high-temperature annealing steps used to activate the dopants in between the dielectric and metal gate deposition steps, Intel is able to maintain a good workfunction metric for the electrode of its pFET transistor, which he said was 51% faster than the previous generation.

The hafnium-based gate dielectric has a 1 nm equivalent oxide thickness (EOT) for both n- and p-type transistors, with a 7 Å interfacial layer, which Mistry referred to as a “transition layer.” Although Intel does not provide its inversion thickness, Mistry said in an interview that the difference between the EOT and Tinv “is about 4 Å, plus or minus 1.” The physical thickness of the HK layer was 18-20 Å, which is thick enough to provide what Mistry said was a 25× improvement in NMOS leakage current, compared with SiO2, and a 3× improvement in PMOS leakage.

The 35 nm gate length transistor has an nFET drive current of 1.36 mA/µm at 1 V operation, which he said was a 12% improvement over the 65 nm process. By increasing the level of germanium in the embedded silicon germanium (eSiGe) stressors from 17% at the 90 nm generation to 23% at 65 nm to 30% at 45 nm, Intel has boosted pFET performance considerably, with a 3× improvement in hole mobilities. That results in a 1.07 mA/µm drive current for the pFET, which Mistry said is “by far, the highest performing PMOS transistor.” Compared with the 65 nm pFET, the 45 nm pFET is 51% faster.

*** The stronger pFET is causing Intel’s design teams to consider the mix of NOR gates, which rely on the nFETs, and NAND gates, which are more pFET-dependent. "With a higher beta ratio [between n- and pFET performance] of 1.3, we can tell our designers up front so they can take advantage,” he said.

For a gate with a fanout of two, the switching speed is 5.1 ps.

In a post-session interview, Mistry said the metal gate-last approach produces a better pFET technology than the gate-first approach. “There has never been a high-performance pFET produced with a gate-first approach." The use of a metal gate helps improve threshold voltage (Vt) pinning and gets rid of the poly depletion problem that had robbed performance. With an oxide poly gate stack, “We were running out of atoms,” Mistry said, making the move to HKMG imperative.

In an outline of the process flow, Mistry said after the silicon-germanium stressors are deposited, a dummy poly gate is removed, which aids in the formation of pFET transistor and retains strain in the nFET transistor.

At later conferences, Intel will describe its patterning technology, which includes double patterning steps at one or more of the critical mask levels using dry 193 nm lithography. “We achieved an amazing fidelity despite using dry lithography,” Mistry said.


http://www.semiconductor.net/article/CA6512230.html?industryid=47298
 
Já não vejo a hora de serem comercializados os Q9450...
Este levou-me a mudar de ideias em relação ao Q6600, apesar de ser provisório este CPU que tenho actualmente até aleija, tá a limitar-me o sistema que é uma coisa parva...
Eu sei o que queres dizer :Sad_anim: D915 aqui
Quanto irá ser o de entrada de gama dos 45nm, alguma previsão?
 
Intel to delay launch of three 45nm quad-core CPUs on poor AMD performance

Intel has recently adjusted its product strategy and will postpone three 45nm quad-core CPUs that were originally scheduled to launch in January next year, according to sources at motherboard makers.

Intel has already notified its partners that it will push back the launch of the three CPUs to February or March next year, depending on AMD's schedule for triple-core and the upcoming Phenom CPUs.

Launching the CPUs now will not benefit Intel much in its battle with AMD, while they could cause damage to Intel's 65nm quad-core CPUs, therefore the company has decided it is in no rush to release new products until AMD is able to present more of a threat.

The three CPUs that Intel plans to delay are the Core 2 Quad Q9300, Q9450 and Q9550, added the sources.

Intel commented that its launch of 45nm quad-core CPUs for desktops is on track for first quarter 2008, but declined to disclose a specific time-frame.
http://www.digitimes.com/mobos/a20071218PD212.html
 
Já começa.

É para evitar este tipo de medidas que é essencial a existência de concorrência, para haver movimento no mercado.

Os problemas do Phenom e da AMD em geral são a oportunidade perfeita para a Intel despachar mais stocks das actuais CPU's de 65nm, ao mesmo tempo que acumula inventário das versões de 45nm, permitindo "inundar" o mercado na altura certa e empreender outra guerra de preços.

Não me admira nada esta atitude.
Falta de concorrência à altura dá nisto.
 
lol...os 3 quad cores, são os que vao ser mais vendidos...a amd está má, mas vamos a ver, as lojas nao expoem sequer a maioria dos produtos da amd nos seus sites, já nem falo em stock, assim e dificil...se as lojas tivessem mais produtos Amd nos seus sites, acredito que havia gente que os comprava.
 
Bem, a ser verdade essa noticia, nao vou esperar por Janeiro/Fevereiro para fazer o upgrade.. Senão fico à espera eternamente.

Quando não há concorrência, é isto que acontece.
 
lol...os 3 quad cores, são os que vao ser mais vendidos...a amd está má, mas vamos a ver, as lojas nao expoem sequer a maioria dos produtos da amd nos seus sites, já nem falo em stock, assim e dificil...se as lojas tivessem mais produtos Amd nos seus sites, acredito que havia gente que os comprava.

Para isso é necessário que existam processadores nos distribuidores...
 
Wow. They are in big trouble.

No significant quantities of B3 Barcs expected until end of Q1.

10-20% perf hit with "fix" to B2. Impacts lower speeds.

Seems to me that AMD should be publicly *recalling* all K10 parts, including Phenom.

Intel is going to take virtually all of their server share over the next few months.

---------------

http://techreport.com/discussions.x/13721

Chip problem limits supply of quad-core Opterons
by Scott Wasson — 1:49 PM on December 3, 2007

AMD's quad-core "Barcelona" Opterons have been notably difficult to find since their introduction two months ago, and The Tech Report has learned that a chip-level problem has impacted the supply of these chips to both server OEMs and distribution channel customers.

Chipmakers refer to chip-level problems as errata. Errata are fairly common in microprocessors, though they vary in nature and severity. This particular erratum first became widely known when AMD attributed the delay of the 2.4GHz version of its Phenom desktop processor to the problem. Not much is known about the specifics of the erratum, but it is related to the translation lookaside buffer (TLB) in the processor's L3 cache. The erratum can cause a system hang with certain software workloads. The issue occurs very rarely, and thus was not caught by AMD's usual qualification testing.

An industry source at a tier-two reseller told The Tech Report that the TLB erratum has led to a "stop ship" order on all Barcelona Opterons. When asked for comment, spokesman Phil Hughes said AMD is shipping Barcelona Opterons now, but only for "specific customer deals." Industry sources have suggested to TR that those deals are high-volume situations involving supercomputing clusters. Such customers may run workloads less likely to be affected by any workarounds for the erratum that reduce L3 cache performance, and those customers could potentially consume hundreds of thousands of CPUs. Our sources indicate, and the current availability picture would seem to confirm, that quad-core Opterons are not shipping to OEMs or the channel more generally.

News of this problem is notable because it confirms that the TLB erratum affects Barcelona server processors as well as Phenom desktop CPUs, and that the problem impacts AMD's quad-core processors at lower clock speeds. AMD's initial public statements about the erratum and the delay of the 2.4GHz Phenom seemed to imply that the issue was closely related to clock frequencies. The Opteron 2300 lineup spans clock speeds from 1.7GHz to 2.0GHz. Those CPUs' north bridge clocks, which determine the frequency of the L3 cache, range from 1.4GHz to 1.8GHz.

The erratum is present in all AMD quad-core processors up to the current B2 revision. AMD has said a revision B3 is in the works and expected in Q1. One source told TR that large quantities of B3 chips might not be available until the end of Q1.

The potential for instability with the TLB erratum can be corrected via BIOS-based workaround, but multiple sources have suggested the BIOS fix involves a substantial performance hit. AMD has publicly estimated the performance penalty for the BIOS fix could be around 10%, and one source pegged the penalty at 10-20%. AMD has acknowledged that the TLB erratum particularly affects virtualization, and industry sources say the performance hit from the fix may be most severe with virtualization, as well. Server administrators responsible for virtualized environments will probably want to wait for the B3-rev CPUs before upgrading.

TR has attempted to confirm the impact of the BIOS-based fix, but the BIOS for the SuperMicro H8DMU+ motherboard used in our review of the Barcelona Opterons has not been updated since mid-September and doesn't appear to include the TLB erratum workaround.

Linux users may have another option in the form of a patch for that operating system's kernel. Sources estimate this patch's performance hit at less than one percent, but it comes with several caveats. At present, the patch purportedly only applies to the 64-bit version Red Hat Enterprise Linux, Upgrade 4. Customers must sign a non-disclosure agreement in order to obtain the patch, and will be responsible for supporting it themselves. The patch doesn't currently appear to be available via Red Hat's regular support channels.

At present, Microsoft doesn't offer a Windows hotfix to address the problem, and our sources were doubtful about the prospects for such a patch. CPU makers have oftentimes addressed errata via updates to the processor's microcode, but such a fix for this problem also appears to be unlikely.

http://www.xtremesystems.org/forums/showthread.php?t=168021


Se calhar é por causa disto!? :rolleyes:
 
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