Processador IBM Power9

[Dark Kaeser]

Big Blue Aims For The Sky With Power9

As it turns out, IBM will be delivering four different variants of the future Power9 chip, as Brian Thompto, senior technical staff member for the Power processor design team at the company, revealed

...

With the Power9 chip, there will be the Power9 SO (short for scale out) variant for machines aimed at servers with one or two sockets, due in the second half of 2017, and the Power9 SU (short forscale up) that will follow in 2018 for machines with four or more sockets and, we think, largely sold by IBM itself for its customers running its own AIX and IBM i operating systems.

In addition to the different core counts and memory options, IBM is making the Power9 SO and Power9 SU chips available with two different levels of simultaneous multithreading, SMT4 with up to four virtual threads per core and SMT8 with up to eight virtual threads per core.

http://www.nextplatform.com/2016/08/24/big-blue-aims-sky-power9/

O artigo acima não tinha todas imagens da apresentação pelo usei as imagens do artigo da computerbase.de

 

[Dark Kaeser]

and Thompto says that the Power9 pipeline was shorter from fetch to compute by five cycles compared to the Power8 core and had better branch prediction. The SMT4 core can do 64 instructions per cycle and the SMT8 core can do twice that at 128 instructions per cycle. The end result of all of the tweaks in the microarchitecture is a leaner and stronger core.

The Power9 chip is the first chip from IBM to support the Power 3.0 instruction set, which has a number of tweaks to it. First of all, the new ISA definition supports 128-bit quad-precision floating point math that is compliant with the IEEE 754 standard and, importantly, is useful for certain financial services and security applications that require higher precision floating point math. The new ISA also supports 128 bit decimal integer math, which is useful with databases and anything that is doing money math. IBM has also added a single-instruction random number generator, which is important for all kinds of simulations that require lots of randomness (it took more than one cycle to do this with the Power8 chips).

I/O

 

[Dark Kaeser]

First Look at Zaius Server Platform from Google, Rackspace Collaboration

https://blog.rackspace.com/first-look-zaius-server-platform-google-rackspace-collaboration


Introducing Zaius, Google and Rackspace’s open server running IBM POWER9

The specifications
Zaius is a dual-socket platform based on the IBM POWER9 Scale Out CPU. It supports a host of new technologies including DDR4 memory, PCIE Gen4 and the OpenCAPI interface. It’s designed with a highly efficient 48V-POL power system and will be compatible with the 48v Open Rack V2.0 standard.

https://cloudplatform.googleblog.co...ackspaces-open-server-running-IBM-POWER9.html


Já vem com o, há dias anunciado, OpenCAPI, que permite conectar vários aceleradores:

http://www.anandtech.com/show/10759/opencapi-unveiled-amd-ibm-google-more

 

[Dark Kaeser]

Da conferência Hot Chips 30, a variante Scale UP do Power 9







até 16 sockets


https://www.servethehome.com/ibm-power9-hc30/


IBM FINISHES POWER9 SYSTEMS ROLLOUT WITH BIG IRON
https://www.nextplatform.com/2018/08/13/ibm-finishes-power9-systems-rollout-with-big-iron/

 

[Nemesis11]

até 16 sockets

Acho que o Power9 está muito interessante, especialmente tudo o que está relacionado com I/O. Ele é uma besta a esse nível (Esquecendo o que existe no mercado de Mainframes).
No entanto o suporte para 16 sockets, em si, não é "nada do outro mundo".
A Intel, só suporta 8 sockets, com as suas soluções, no entanto third parties suportam mais que isso. Tens o HP Superdome X a suportar 16 sockets, o HP Superdome Flex e o Huawei KunLun a suportar 32 sockets.

 

[Dark Kaeser]

Supermicro P9DSU-C Based IBM POWER9 Server Spotted with Xilinx FPGAs

https://www.servethehome.com/supermicro-p9dsu-c-based-ibm-power9-server-spotted-with-xilinx-fpgas/

basicamente usam o mesmo layout dos sistemas da Intel Xeon e AMD EPYC, neste caso para uma board com Power9, e ao invés de um GPU da Nvidia ou AMD usam o FPGA da Xilinx.

 

[Nemesis11]

A board micro-ATX Blackbird, da Raptor, com Power 9, para um mercado mais comum:

https://twitter.com/GinaLKing/status/1062557483661737984

 

[LSeven]

Trabalho com máquinas destas, e são grandes bestas, principalmente quando associadas a storages. A entrada de gama leva até 20 cores e 1 Tb de ram, mas as estrelas na minha opinião, são os modelos 922 com máximo de 24 cores e até 4Tb de RAM. Eu trabalho mais com os modelos virados para AIX / IBM i, mas a L922 dedicada para Linux é um monstro com um preço relativamente acessível. Os modelos Power9 também são muito competitivos (e com modelos específicos) para SAP HANA e Deep Learning / AI frameworks.

 

[Nemesis11]

Coloco isto aqui, porque este formato aparece a partir do mercado Power 9.

Serial Attached Memory

Este formato tem várias vantagens:

• A mesma performance com 4 vezes menos o mesmo número de pins.
• Abstracção para o sistema do tipo de memória. O processador só vê uma ligação serial para a RAM. Não faz ideia do que está por trás.
• O controlador de memória passa a estar nos DIMMs e não no processador.
• O SOC é mais pequeno ao mesmo SOC para aceder a 2 canais de memória actuais.
• Maior capacidade de memória.
• Maior flexibilidade. Por exemplo, será possível ter a RAM fora do chassis do sistema.

https://www.servethehome.com/microchip-smc-1000-for-the-serial-attached-memory-future/

É possível que vá ter concorrência de futuros formatos de memória CXL e GEN-Z, com a mesma filosofia.

 

[SideWalker]

Enfiar o controlador no módulo deve é encarecer bastante a memória, não ?

 

[Neural]

Acho que vai depender da capacidade de cada stick, mas se o controlador está na memória, já não vai ter que estar na northbridge/cpu...
A lógica dos controladores de memória não é muito complicada, não acredito que sejam chips caros. Além disso, terá provavelmente latência baixas...

 

[Kn0xx]

Fiquei estupefacto com as diferenças no tradicional DDR e o OMI interface. e claro está AMD deve estar a planear estas coisas, caso tenha massificação no mercado o suficiente. é um salto gigante, passar para 5~10nm de latências na DDR.
Portanto, next-gen domestico passa a ter buffered memory.

 

[Dark Kaeser]

A AMD tem patenteado várias coisas no domínio da memória, tens um bom resumo e links dos mesmos neste post do twitter

https://twitter.com/Underfox3/status/1125284546969206784

 

[Nemesis11]

A IBM acabou de tornar Open Source a POWER ISA. Contribuiu o OpenPOWER à Linux Foundation.

The Next Step in the OpenPOWER Foundation Journey

Today marks one of the most important days in the life of the OpenPOWER Foundation. With IBM announcing new contributions to the open source community including the POWER Instruction Set Architecture (ISA) and key hardware reference designs at OpenPOWER Summit North America 2019, the future has never looked brighter for the POWER architecture.

OpenPOWER Foundation Aligns with Linux Foundation
The OpenPOWER Foundation will now join projects and organizations like OpenBMC, CHIPS Alliance, OpenHPC and so many others within the Linux Foundation. The Linux Foundation is the premier open source group, and we’re excited to be working more closely with them.

Since our founding in 2013, IEEE-ISTO has been our home, and we owe so much to its team. It’s as a result of IEEE-ISTO’s support and guidance that we’ve been able to expand to more than 350 members and that we’re ready to take the next step in our evolution. On behalf of our membership, our board of directors and myself, we place on record our thanks to the IEEE-ISTO team.

By moving the POWER ISA under an open model – guided by the OpenPOWER Foundation within the Linux Foundation – and making it available to the growing open technical commons, we’ll enable innovation in the open hardware and software space to grow at an accelerated pace. The possibilities for what organizations and individuals will be able to develop on POWER through its mature ISA and software ecosystem will be nearly limitless.

The Impact of an Open POWER ISA and Open Source Designs
We’ve heard in the past that developing a full featured core like POWER can be complicated – but that’s not necessarily the case. In fact, we believe the open source community can leverage the contributions made by IBM rather quickly.

In addition to open sourcing the POWER ISA, IBM is also contributing a newly developed softcore to the community. In a very short time, an IBM engineer was able to develop a softcore on the POWER ISA, and get it up and running on a Xilinx FPGA. This softcore implementation is being demonstrated this week at OpenPOWER Summit North America.

“This is the first tangible outcome of the opening of the POWER ISA,” said Mendy Furmanek, President, OpenPOWER Foundation and Director, OpenPOWER Processor Enablement, IBM. “It’s an example of the type of innovation that can be brought forward by the community as a result of newly open-sourced contributions.”

IBM is also contributing reference designs for OpenCAPI and Open Memory Interface (OMI) to the open source community. OpenPOWER Foundation and OpenCAPI Consortium member Microchip Technology was recently awarded Best Of Show at Flash Memory Summit 2019 for its newly announced serial memory controller, which leverages interface designs IBM is contributing.

While these designs are architecture-agnostic, they will help to grow and advance the OpenPOWER ecosystem. OpenPOWER Foundation partners including IBM and Google share their perspectives on the news in Microchip’s announcement of the SMC 1000 8x25G.

https://openpowerfoundation.org/the-next-step-in-the-openpower-foundation-journey/

Em principio, com a ISA a tornar-se open source, qualquer empresa pode criar um CPU POWER.

 

[Neural]

Muito interessante...