AMD Initiates Shipments of 90nm Microprocessors?

AMD Initiates Shipments of 90nm Microprocessors?

Pictures of AMD64 Chips at 90nm Hit the Web

Advanced Micro Devices might have started to ship its first microprocessors made using 90nm silicon-on-insulator process technology to certain clients, as may be suggested from a picture of an AMD64 chip that is reported to be produced using 90nm fabrication process.

VR-Zone web-site who published the photo said that AMD Athlon 64 processor in the picture was code-named Oakville. According to AMD’s recent roadmap, the Oakville core is designed for Mobile Athlon 64 processors.

The web-site reports that desktop flavour of Oakville code-named Winchester will have extremely small die of 83 square millimeters. Both chips will incorporate 512KB of L2 cache, but it is not clear whether the chips sport dual-channel or single-channel memory controllers.

According to the recently unveiled roadmap, the Sunnyvale, California-based chipmaker plans to release a number of AMD Opteron processors code-named Athens, Troy and Venus, a Mobile Athlon 64 processor known as Oakville and a desktop Athlon 64 processor code-named Winchester produced using 90nm fabrication process in the second half of the year. The initial commercial shipments of AMD64 chips produced at 90nm nodes are officially said to commence in the third quarter of 2004.

In the first half of next year AMD will release the successor of its AMD Athlon 64 FX chip with core code-named San Diego along with a lineup of mobile microprocessors. In the second half of the year the company will release dual-core chips. AMD believes that the current AMD Athlon 64 FX microprocessor made using 130nm technology will be able to scale for at least one speed-bin required to compete successfully with the rival Intel Corp..

According to unofficial sources, AMD’s Athlon 64 FX-57 processor at 2.80GHz made using 90nm Silicon-on-Insulator process technology will be released in Q2 2005. A slightly slower AMD Athlon 64 FX-55 chip at 2.60GHz will be available in Q4 2004.

In the second half of next year AMD will initiate production of dual-core processors for various market segments using 90nm SOI process.

Representatives from Advanced Micro Devices declined to comment on the report, but said the company started shipments of samples products using 90nm process technology in Q2 2004 and is on track to begin volume commerical production of such devices in Q3 2004.

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Our good friend, Boss50 has got his hands on the Athlon 64 3000+ (2.0Ghz) based on 90nm "Oakville" core packed with 512KB of L2 cache. The desktop version of 90nm Athlon 64 is based on "Winchester" core has much smaller die size at 83mm2 compared to 144mm2 of the "Newcastle" core. The revision stepping of the upcoming 90nm Athlon 64 desktop and mobile processors is "D0" compared to the current "CG" stepping that denote a silicon change due to die shrink.

AMD is going to launch the 90nm Athlon 64 desktop processors in Socket 939 during Sept/Oct period with the highest speed grade, Athlon 64 4000+ (2.6Ghz) at launch and other lower speed grades like 3000+, 3200+, 3500+ and 3800+. AMD is also going to launch three low power mobile Athlon 64 processors (35W TDP) based on 90nm "Oakville" core at the same time with speeds from 2700+ (1.6Ghz), 2800+ (1.8Ghz) and 3000+ (2Ghz) in 754 package.

Correction : This is actually low power mobile Athlon 64 3000+ based on 90nm "Oakville" core

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Slider disse:

Não tem HS? wtf......

Ou tem e foi retirado para mostrar o core?

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The 90nm A64 is not a simple die shrink but features several enhancements, such as:

* Improved hardware data prefetch mechanism
* Increased number of writing combine buffers (D0 stepping A64's can now combine up to four non-cacheable streams compared to 2 o*n the C0 and CG stepping A64's)
* Improved o*n-die memory controller with more advanced open page policy
* O*n-die thermal throttling
* Black Diamond Low-K technology (slower less power hungry transistors in less used sections and faster and more power hungry transistors in frequently used sections of the cpu)
* Full SSE3 implementation (?)


Furthermore the new D0 A64s can convert LEA intructions into ADD instructions in certain situations wich can then be executed in a single clock cycle wich should also give a performence boost in some apps.

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